Münster 2002 – scientific programme

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HK: Physik der Hadronen und Kerne

HK 14: Poster Session: Instrumentation and Applications

HK 14.14: Poster

Tuesday, March 12, 2002, 10:30–12:45, Foyer Chemie

Implementation of a RISC CPU in FPGA
— •A. Danasino, H. Fischer, J. Franz, A. Grünemaier, S. Hedicke, F.H. Heinsius, M. von Hodenberg, F. Karstens, W. Kastaun, K. Königsmann, J. Reymann, T. Schmidt, H. Schmitt, and J. Worch — Fakultät für Physik, Universität Freiburg

The CATCH modules are the central building blocks of the readout system of the COMPASS experiment. The CATCH acts as a local event builder, adding information useful for the localization of the signals sent from the detectors. The CATCH is designed with several programmable logic devices (FPGA and CPLD). For monitoring and control of the data flow a complete system-on-a-chip design is implemented in one FPGA. It includes a 16 bit RISC processor which is clocked with 10 MHz. The microprocessor core is derived from the XSOC project developed by Jan Gray of Gray Research LLC. Very flexible programming can be done in integer C which is translated to the MIPS based instruction set of the microprocessor. It can communicate to all other FPGAs on the CATCH, reset and monitor mezzanine cards and send serial initialization data to the front end boards. It can drive a four character display on the front panel of the CATCH module. For further information: http://hpfr02.physik.uni-freiburg.de/projects/compass/electronics
This project is supported by the BMBF.