Göttingen 2012 – wissenschaftliches Programm

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T: Fachverband Teilchenphysik

T 78: Trigger

T 78.5: Vortrag

Freitag, 2. März 2012, 09:30–09:45, VG 0.111

An FPGA based demonstrator for a topological processor in the future ATLAS Level1-Calo trigger — •Eduard Simioni, Andreas Ebling, Bruno Bauss, Ulrich Schäfer, Volker Büscher, Reinhold Degele, Weina Ji, Carsten Meyer, Sebastian Moritz, Stefan Tapprogge, and Volker Wenzel — Universität Mainz, Staudingerweg 7, 55128 Mainz

In 2014 LHC will collide proton bunches at the nominal energy of 14 TeV with an increased luminosity up to 3×1034 cm−2 s−1. To keep the trigger efficiency high in spite of the increase in event rate, an extra electronics module will be added in the L1-Calo trigger chain: the Topological Processor (TP).

With the TP, topological event information currently processed at Level2 will be available within the L1-Calo latency budget. Information on angles between jets and/or leptons can be used to reduce the trigger rates.

From a hardware point of view the TP requires fast optical I/O and large bandwidth. This is provided by the most advanced FPGAs on the market (with embedded multi Gb/s transceivers) and multi Gb/s opto converters. These technologies have been implemented into an advancedTCA form factor board, "GOLD", as a demonstrator for the ATLAS TP.

In this presentation the tests performed on the "GOLD" demonstrator are summarized, including a characterization of the high speed links (opto converters and transceivers) and tests of topological algorithms in their firmware incarnation for measuring latency and performance.

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