Dresden 2013 – scientific programme
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T: Fachverband Teilchenphysik
T 76: DAQ, Trigger und Elektronik 1
T 76.1: Group Report
Wednesday, March 6, 2013, 16:45–17:05, GER-039
The Belle II PXD Data Acquisition and Reduction System — •Sören Lange1, Thomas Geßler1, Wolfgang Kühn1, Haichuan Lin2, Zhen’An Liu2, David Münchow1, Björn Spruck1, Hao Xu2, and Jingzhou Zhao2 — 1II. Physikalisches Institut, Justus-Liebig-Universität Giessen — 2IHEP Beijing, for the Belle II Collaboration.
The Belle II DEPFET pixel detector (PXD) will deliver high data rates of up to 21.6 Gbytes/s for 3% detector occupancy. Data of this high rate must be buffered for 5 seconds, corresponding to the HLT (High Level Trigger) latency, and then a region-of-interest (ROI) filter is applied to reduce the data rate by a factor of ≥10 by charged track extrapolation from other detectors (SVD, CDC). The PXD readout system is based upon ATCA (Advanced Telecommunications Architecture). The 3rd PCB iteration uses a concept with a xTCA carrier board (with a Virtex-4 FX60 FPGA for ATCA backplane routing) and 4 AMC modules (each with a Xilinx Virtex-5 FX70T FPGA). The FPGA firmware implementation comprises a receiver core for the high speed optical links (≤6.25 Gbps), a buffer management with lookup of ≤270.000 pointers/s, DDR2 memory write (native port interface, ≥1.5 Gbytes/s), Gigabit ethernet (UDP stack in VHDL) and a parallized ROI selection algorithm. Test results of all the componentes will be presented. This work is supported by BMBF under grant ♯05H10RG8.