Dresden 2026 – scientific programme
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HL: Fachverband Halbleiterphysik
HL 17: Quantum Dots and Wires: Rings, Wires and Transport
HL 17.9: Talk
Tuesday, March 10, 2026, 11:45–12:00, POT/0251
CMOS Compatible Short-Channel Junctionless Nanowire Transistors — •Sayantan Ghosh1,2, Alessandro Puddu1,2, Slawomir Prucnal1, Yordan M. Georgiev1, Ahmad Echresh1, and Artur Erbe1,2 — 1Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, 01328 Dresden, Germany — 2Technische Universität Dresden, 01069 Dresden, Germany
The demand for miniaturized, high-speed, and energy-efficient electronics is pushing conventional planar transistors to their scaling limits, where short-channel effects and fabrication complexity constrain performance. Junctionless nanowire transistors (JNTs) offer a promising alternative through simplified architecture, strong electrostatic control, and CMOS compatibility. Using uniformly doped channels and eliminating pn-junctions, JNTs reduce process complexity and improve scalability for next-generation nanoelectronics. In this work, short-channel silicon JNTs were fabricated on SOI substrates using a CMOS-compatible top-down method. The devices use 20 nm-wide n-type Si nanowires with channel lengths from 1000 nm to 50 nm. Back-gate operation shows clear ambipolar behaviour, while top-gate operation yields the unipolar response characteristic of true JNTs. The 50 nm device achieves a current on/off ratio > 5 orders of magnitude and a subthreshold swing of around 200 mV/dec, demonstrating strong potential for low-power nanoscale technologies.
Keywords: Junctionless; CMOS; JNT; short-channel