Dresden 2026 – scientific programme
Parts | Days | Selection | Search | Updates | Downloads | Help
HL: Fachverband Halbleiterphysik
HL 23: Transport Properties
HL 23.3: Talk
Wednesday, March 11, 2026, 10:00–10:15, POT/0051
Influence of Thermal Annealing on CMOS-Integrated Graphene Field-Effect Transistors — •Daniel Nickel1, Daniele Capista1, Rasuole Lukose1, Christian Wenger1,2, and Mindaugas Lukosius1 — 1IHP - Leibniz Institute for High Performance Microelectronics, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany — 2BTU Cottbus Senftenberg, Platz der Deutschen Einheit 1, 03046 Cottbus, Germany
This work investigates the influence of consecutive annealing on CMOS-integrated graphene field-effect transistors (GFETs) with annealing temperatures (Ta) from 150 ∘C up to 300 ∘C. The GFETs were fabricated on 200 mm SiO2/Si wafers with Pd/Au and Ni edge contacts, tungsten backgate and Si3N4 passivation. Annealing was carried out in 150 sccm nitrogen flow for 1 h using a 10 ∘C/min ramp. Electrical transfer measurements show that maximum p- and n-type field-effect mobilities occur at Ta = 200 ∘C for Pd/Au (µp ≈ 950 cm2/Vs, µn ≈ 1650 cm2/Vs) and at Ta = 150 ∘C for Ni (µp ≈ 450 cm2/Vs, µn ≈ 890 cm2/Vs). Raman analysis indicates an improved graphene quality with increasing Ta. Raman mapping reveals that for Pd/Au, the FWHM of the 2D peak reaches a minimum at Ta = 200 ∘C, followed by a slight increase in compressive strain at higher Ta. For Ni, broader 2D and G peak distributions and a reduction in p-doping with increased Ta is observed. Raman data measured near the Ni contacts reveal reduced p-doping, whereas doping near the Pd/Au contacts remains largely unaffected. Funding was provided by EU Horizon 2020 Graphene Flagship grants 101189797 and 101120938.
Keywords: Graphene; Field-effect transistors; Carrier mobility; Annealing; CMOS Integration