Dresden 2026 – scientific programme

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QI: Fachverband Quanteninformation

QI 16: Quantum Software

QI 16.9: Talk

Thursday, March 12, 2026, 12:15–12:30, BEY/0245

Reducing the cost of gate-set tomography of superconducting quantum processors — •Martin Koppenhöfer, Michael Krebsbach, and Thomas Wellens — Fraunhofer-Institut für Angewandte Festkörperphysik IAF, Tullastraße 72, 79108 Freiburg, Deutschland

Gate errors remain one of the biggest obstacles on the road towards scalable quantum processors. Obtaining a precise understanding of these errors and of their origin is a necessary step for hardware improvements and error mitigation. In principle, gate-set tomography protocols allow one to obtain a detailed, self-consistent picture of quantum processors including state-preparation and measurement steps. However, a drawback of these protocols is that they become computationally very costly when multi-qubit gates are analyzed, leading to a very large set of germ circuits as well as an exponential growth of the initial states that need to be prepared and measurements that need to be performed.

In this talk, we present a modified approach to gate-set tomography that exploits different gate fidelities for single- and two-qubit gates to reduce the number of germ circuits and fiducial states. For two-qubit gate-set tomography, this approach reduces the number of required experiments by more than an order of magnitude and thus speeds up gate-set tomography protocols. We demonstrate this new technique on a superconducting quantum processor.

Keywords: Gate Set Tomography; Superconducting Qubits; Scalable benchmarking techniques; Gate errors; State preparation and measurement errors