Erlangen 2026 – scientific programme

Parts | Days | Selection | Search | Updates | Downloads | Help

T: Fachverband Teilchenphysik

T 6: Electronics, Trigger, DAQ I

T 6.1: Talk

Monday, March 16, 2026, 16:15–16:30, KH 00.023

Next-Generation Readout ASIC for DEPFET Pixel Detectors in 65-nm CMOS — •Vasiliki Gogolou, Hans Krüger, and Jochen Dingfelder — University of Bonn, Germany

The continued evolution of particle-physics experiments places increasing demands on the performance, efficiency, and integration density of readout electronics. As detector systems grow in channel count and as data rates accelerate, high-quality, low-noise readout chains become essential to preserve the precision of the underlying sensor technology. DEPFET (Depleted p-channel field effect transistor) pixel sensors play a key role in this landscape with successful applications ranging from high-energy physics vertex detectors such as those for the ILC and Belle II to advanced medical imaging systems. This work presents a next-generation readout integrated circuit for DEPFET matrices, implemented in a state-of-the-art 65-nm CMOS process node. The transition to a smaller feature size enables improved power-area efficiency while maintaining low noise. Each channel integrates a cascode transimpedance amplifier and a compact single-ended-to-differential stage, optimized to fully drive the input range of a high-speed, low-power SAR ADC (successive-approximation register analog-to-digital converter). The readout architecture is specifically designed to interface seamlessly with such ADCs, enabling a system that meets stringent constraints on power density and pixel pitch while delivering the precision required for future high-rate, high-resolution experiments.

Keywords: analog front-end; amplifier; DEPFET; readout