Regensburg 1998 – wissenschaftliches Programm
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HL: Halbleiterphysik
HL 28: Epitaxie
HL 28.8: Vortrag
Donnerstag, 26. März 1998, 12:15–12:30, H14
REDUCTION OF THERMAL BUDGET FOR Si/SiGe EPITAXY FOR CMOS INTEGRATION OF HETEROJUNCTION BIPOLAR TRANSISTORS — •Dirk Wolansky, K. Blum, and B. Tillack — Institute for Semiconductor Physics, Walter-Korsing-Str. 2, 15230 Frankfurt (Oder)
The CMOS integration of Si/SiGe heterojunction bipolar transis- tors (HBTs) requires a low thermal budget for epitaxy. We lo- wered this budget by a reduction of hydrogen prebake temperature for native oxide removal by different ex situ clean variants: A - our standard RCA (Piranha/SC1/DHF/SC2(75 degrees C)) as a ref- erence, B - modified RCA (SC2(30 degrees C)) and C - RCA fol- lowed by a DHF dip. The thermal budget was reduced from 900 degrees C and three seconds of variant A to 830 degrees C and three seconds for variant B. A reduction to 750 degrees C and three seconds was achieved for variant C. These temperatures de- pend proportionally on the oxide thickness on the wafer surfaces. All clean variants were evaluated in terms of collector to emit- ter leakage current ICEs of Si/SiGe HBT, characterizing the quality of epitaxial layers very sensitively. Variants B and C result in an acceptably high yield in ICEs enabling a reduc- tion in the thermal budget of the post CMOS HBT integration.