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HL: Halbleiterphysik

HL 54: Bauelemente II

HL 54.2: Talk

Friday, March 28, 2003, 12:00–12:15, BEY/81

Patterning of 25 nm wide Silicon Ridges for Vertical Double-Gate MOSFETs — •Stefan Trellenkamp, Jürgen Moers, André van der Hart, Peter Kordoš, and Hans Lüth — Institute of Thin Films and Interfaces-1, Forschungszentrum Jülich, 52425 Jülich

The downscaling of MOSFET devices has progressed in an exponential way during the last thirty years. One of the main problems with miniaturisation of device structures is the lithography limitation. Many device concepts require silicon ridges with high aspect ratio. Our concept of a vertical double gate MOSFET needs for the active region silicon ridges 300 nm in height and less than 30 nm in width. Electron beam lithography and reactive ion etching were used to produce these lines. In order to define the structures hydrogen silsesquioxane (HSQ) was used as electron beam resist. 23 nm wide and 110 nm high lines in HSQ were obtained. These structures where transferred by dry etching with a HBr/O2-plasma and an ICP-source (inductive coupled plasma). This resulted in 25 nm wide and 330 nm high silicon ridges.