Berlin 2005 – wissenschaftliches Programm

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DS: Dünne Schichten

DS 10: FV-internes Symposium „Anorganische Dielektrika für die künftige Mikro- und Nanotechnologie"

DS 10.5: Hauptvortrag

Samstag, 5. März 2005, 13:00–13:45, TU HS110

Advance MOSFET gate dielectrics for high-performance microprocessors: Materials selection and analytical challenges — •E. Zschech¹, H.-J. Engelmann ¹, K. K Dittmar ¹, S. Ohsiek ¹, B. Tracy², E. Adem ², A. Myers², S. Robie ², M. Sidorov ², and J. Bernard ² — ¹AMD Saxony LLCCo. KG, Dresden, Germany — ²Spansion Inc., Sunnyvale/CA, U. S.

According the 2003 ITRS roadmap [1], high-performance microprocessors (HP-MPUs) are driving the continuous shrinking of metal-oxide-semiconductor (MOS) feature sizes. The scal-ing down of the HP-MPU physical gate length follows a two-year cycle with a scaling factor of 0.7 until 2005 and switches to a three-year cycle thereafter, leading to 10 nm gates in 2015. The traditional down-scaling of MOS transistors leads to performance limitations that have to be overcome by the introduction of new materials in the gate stack, which result in new and exciting challenges to solid-state physicists and materials scientists. For leading edge logic products, the transistor performance can be further increased by metal oxide gate dielectrics with a high dielectric constant (high-k materials). The particular need for low-leakage devices is driving the implementation of high-k gate dielectric materials during the next couple of years - one of the key challenges for materials research and process inte-gration. However, until real high-k dielectrics will be introduced into the CMOS process, sili-con oxynitrides will being used as an interim solution. In this paper, material transitions that are necessary to improve the product performance and to maintain the product reliability of HP-MPUs are highlighted. Particularly, the reduction of gate leakage currents by the implementation of high-k materials (at first silicon oxynitrides, followed by metal oxides) for gate dielectrics in MOS transistors is discussed. The need of leading-edge analytics for the study of fundamental integration, performance and reliability issues of metal oxides and for the optimization silicon oxynitride thin films is demonstrated.

[1] International Technology Roadmap for Semiconductors (ITRS): Semiconductor Interna-tional Association (SIA), 2003 Edition, http://public.itrs.net