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HK: Fachverband Hadronen und Kerne
HK 30: Accelerators and Instrumentation I
HK 30.1: Group Report
Tuesday, March 17, 2009, 14:00–14:30, H-ZO 80
FPGA Based Compute Nodes for Trigger and Data Acquisition in HADES and PANDA — •Ming Liu1, Johannes Lang1, Zhen'an Liu2, Hao Xu2, Qiang Wang1, Dapeng Jin2, Sören Lange1, Johannes Roskoss1, Andreas Kopp1, David Münchow1, and Wolfgang Kühn1 — 1II. Physikalisches Institut, Universität Giessen, Germany — 2IHEP Beijing, China
Modern experiments in hadron and nuclear physics such as HADES and PANDA at FAIR require high performance trigger and data acquisition solutions which - in the case of PANDA - can cope with more than 10^7 reactions/s and data rates in the order of 100 GB/s.
As an universal building block for such high performance systems, an ATCA compliant FPGA based Compute Node (CN) has been designed and built. Sophisticated online filtering algorithms can be executed on 5 XILINX Virtex-4 FX60 FPGAs. Each CN features up to 10 GBytes of DDR2 memory. Multiple CNs can communicate via optical links, GBit Ethernet and the ATCA Full Mesh backplane. The total bandwidth of a single CN exceeds 35 GB/s. The system is highly scalable ranging from small configurations in a single shelf to large multi-shelf solutions.
The talk will present the architecture as well as performance results for first algorithms, which have been implemented in the framework of the HADES trigger upgrade.
This talk has been supported in part by BMBF (06 Gi 179 & 180, Internationales Büro) and GSI