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HK: Fachverband Hadronen und Kerne

HK 53: Accelerators and Instrumentation II

HK 53.7: Talk

Wednesday, March 18, 2009, 15:30–15:45, H-ZO 90

Dynamical Partial Reconfiguration for Data Acquisition — •Norbert Abel, Jano Gebelein, and Udo Kebschull — KIP Heidelberg

Xilinx FPGAs like Virtex2, Virtex4 or Virtex5 provide the possibility to be reconfigured partially and dynamically. This means, that parts of the hardware can be exchanged while the rest of the circuit is running untouched. Nowadays, typical applications of dynamical partial reconfiguration (DPR) are streaming, low power, reconfigurable coprocessors and fault tolerance. Furthermore, DPR can help to increase design flexibility and scalability while the design itself becomes smaller at the same time. Regarding to the DAQ (data acquisition) in high energy physic experiments, all these topics are of interest. Unfortunately, today it is still very complex to use DPR, since the developer has to understand the reconfiguration techniques in detail to be able to use DPR. That causes a small usage of DPR in DAQ systems, yet. In the following we want to present a DPR framework that makes it possible to use the complete DPR techniques without going in detail with the underlying technology. Thus, our framework enables regular DAQ developers to use all the advantages coming with partial reconfiguration.