Karlsruhe 2011 – wissenschaftliches Programm
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T: Fachverband Teilchenphysik
T 75: DAQ und Trigger II
T 75.2: Vortrag
Dienstag, 29. März 2011, 17:00–17:15, 30.23: 2-11
FPGA Based Algorithms for Data Reduction at Belle II — •David Münchow, Thomas Geßler, Wolfgang Kühn, Jens Sören Lange, Ming Liu, and Björn Spruck — II. Physikalisches Institut, Universität Gießen
Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e+e − collider with a design luminosity of 8·1035 cm−2s−1.
At Belle II the estimated event rate is ≤30 kHz. The resulting data rate at the Pixel Detector (PXD) will be ≤7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for bufferin and storing the data.
The status of the implementation and performance tests of the memory manager and data reduction algorithm will be presented.
This work is supported by BMBF under grant 05H10RG8.