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Q: Fachverband Quantenoptik und Photonik

Q 35: Poster 2

Q 35.59: Poster

Mittwoch, 14. März 2012, 16:30–19:00, Poster.I+II

Fabrication processes of a segmented surface trap — •Peter Kunert, Daniel Georgen, Michael Johanning, and Christof Wunderlich — Universität Siegen, Naturwissenschaftlich-Technische Fakultät, Dept. Physik, 57068 Siegen, Deutschland

Small dimensions of ion traps are advantageous to build up complex trap-structures and trap-arrays. A promising approach for this is the development of a surface trap. This type of trap consists of an electrode structure reduced to a 2D plane. An important advantage of the surface trap is the possibility to use micro-system technology for its production. We present a possible fabrication procedure of such a trap-chip using clean room technology such as optical lithography, electro-plating and etching. For this purpose a gold-electroplating device was constructed and integrated into an inexpensive small, self-made clean room. 100 to 200 micrometer wide gold-electrode structures with a height of 8.5 micrometer and an inner electrode distance of 10 micrometer are produced onto a sapphire wafer. Also, the integration of the trap-chip into an ultra-high-vacuum-system via a self-made chip-carrier is shown. This carrier is produced using thick-film technology especially and includes electrical low-pass filters directly on the carrier.