Münster 2017 – wissenschaftliches Programm

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HK: Fachverband Physik der Hadronen und Kerne

HK 50: Instrumentation XI

HK 50.2: Vortrag

Donnerstag, 30. März 2017, 17:00–17:15, F 3

Dataflow Lattice QCD Calculations on FPGA Accelerator — •Thomas Janson and Udo Kebschull — Infrastructure and Computer Systems in Data Processing (IRI), Goethe University Frankfurt, Germany

We implement and test algorithms of lattice QCD on FPGA accelerator. To deploy complex algorithms on an FPGA it is crucial to use a high-level language other than VHDL or Verilog. Instead, we use a high-level dataflow based programming language openSPL from Maxeler. This reduces the design effort dramatically while producing more efficient hardware. The algorithm is described as a directed dataflow graph which exposes implicit its parallelism and locality.

We have proven this concept for the Wilson Dirac operator in single precision, where we have described the operator as dataflow graph that collects all nearest neighbor terms and perform all multiplications and additions parallel in one kernel tick. The so described operator fits completely on an Altera Stratix V FPGA and updates for each kernel tick one Spinor.