Parts | Days | Selection | Search | Updates | Downloads | Help

HL: Fachverband Halbleiterphysik

HL 50: HL Poster IV

HL 50.40: Poster

Thursday, March 15, 2018, 19:00–21:00, Poster B

Simulation of morphology and electric behavior of a printed vertical field effect transistor — •Manuel Rommel, Pascal Friederich, and Wolfgang Wenzel — Institute of Nanotechnology, Karlsruhe Institute of Technology, Germany

Decreasing device dimensions is a common strategy to increase field effect transistor performance. In printed electronics, device dimensions are linked to the printing resolution, thus limiting its properties. Therefore, a vertical field effect transistor has been experimentally demonstrated (doi:10.1002/adma.201603858), where channel length is defined by the thickness of the printed layers instead. However, neither the local charge distribution nor the influence of parameter changes on the transistor are easily accessible in experiment.

Therefore, we will show simulation results of domain formation using a Monte Carlo method as well as 3D drift diffusion simulations of the electric behavior of this device architecture. The drift diffusion simulations yield the local charge carrier distribution and electric potential, which show the conduction channel doesn't penetrate the whole system, resulting in ohmic stray currents. A domain formation model was used to generate morphologies exhibiting smaller and larger domain sizes, as they would occur in a slower or faster annealing step in experiment. The simulated transfer curves of these virtual devices show an increased on/off-ratio for smaller domain sizes. A doping concentration sweep yields a dependence of the off-current on doping concentration. These results promise increased performance on smaller domain sizes and the tunability via doping concentration.