Bereiche | Tage | Auswahl | Suche | Aktualisierungen | Downloads | Hilfe

HL: Fachverband Halbleiterphysik

HL 50: Materials and devices for quantum technology III

HL 50.11: Vortrag

Freitag, 31. März 2023, 12:30–12:45, JAN 0027

Design of power efficient digital low-dropout circuit for quantum computers — •Swasthik Baje Shankarakrishna Bhat¹, Alfonso Rafael Cabrera Galicia¹, Arun Ashok¹, Patrick Vliex¹, Andre Zambanini¹, Christian Grewing¹, and Stefan van Waasen^1,2 — ¹Forschungszentrum Jülich GmbH, Germany — ²Universität Duisburg-Essen

Quantum computing is an approach to enable new computing paradigms with qubits as the computing elements that require individual tuning. A limitation in current setups is the number of controllable qubits. To scale the number of qubits, a close integration of control circuits close to the qubits in the cryogenic environment is required. However, to deal with these cryostats* minimal thermal power budget, ultra-low power dissipation is required, also for biasing circuits.

This contribution presents the design and simulation results of a power-efficient digital low-dropout regulator developed with a commercial 22nm FDSOI technology. It is expected that the circuit will enable on-chip biasing for future quantum computers based on Cryogenic Electronics operating at 4 K. Unlike its Analog counterpart integrated Digital LDO is not prone to process and mismatches delivering high efficiency at the same time The circuit concept and the system model investigation performed via Matlab-Simulink will be showed, as well as the expected circuit performance.