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HL: Fachverband Halbleiterphysik
HL 20: Poster I
HL 20.46: Poster
Dienstag, 10. März 2026, 18:00–20:00, P1
Mixed-dimensional Silicon Junctionless Nanowire Transistors with Hexagonal Boron Nitride Gate Dielectrics — •Ahmed Elwakeel1,2, Sayantan Ghosh1,2, Alessandro Puddu1,2, Madhuri Chennur1,2, Slawomir Prucnal1, Yordan Georgiev1, Ahmad Echresh1, and Artur Erbe1,2 — 11Institute of Ion Beam Physics and Materials Research, Helmholtz-Zentrum Dresden-Rossendorf, 01328 Dresden, Germany — 2Technische Universität Dresden, 01069 Dresden, Germany
The investigation of two-dimensional hexagonal boron nitride (hBN) as a gate dielectric arises from the intrinsic limitations of conventional oxide layers in aggressively scaled devices. Owing to its atomically thin structure, excellent insulating characteristics, and inherently clean surface free of dangling bonds, hBN enables improved electrostatic control and effective channel passivation. In Junctionless Nanowire Transistors (JNTs), which remain strong contenders for extending Moore's Law, the use of hBN offers the potential to suppress interface trap states and enhance carrier transport. In this work, a top-down fabrication approach was employed to define the n-type doped silicon nanowires (C = 1E19 cm-3). Two distinct JNT devices were prepared: one with native oxide and another incorporating a thermally grown oxide. Subsequently, exfoliated hBN flakes were dry-transferred onto both samples as a gate dielectric. The hBN-integrated JNTs with thermally grown oxide exhibited pronounced improvements in subthreshold swing, on-state current, and the ION/IOFF ratio.
Keywords: Silicon Junctionless Nanowire Transistors; Hexagonal Boron Nitride; Mixed-dimensional nanoelectronic devices; Top-down fabrication; Electrical characterization