Bereiche | Tage | Auswahl | Suche | Aktualisierungen | Downloads | Hilfe

QI: Fachverband Quanteninformation

QI 11: Implementations IV

QI 11.6: Vortrag

Mittwoch, 11. März 2026, 11:30–11:45, BEY/0245

High-Coherence Superconducting Qubits on Wafer-Scale — •Julius Feigl^{1, 2}, Niklas Bruckmoser^{1, 2}, Leon M. Koch^{1, 2, 3}, David Bunch^{1, 2}, Léa Richard^{1, 2}, Christian Gnandt^{1, 2}, Ivan Tsitsilin^{1, 2, 3}, Anirban Bhattacharjee^{1, 2}, Haiyang Hu^{1, 2}, Vera P. Bader^{1, 2}, Lasse Södergren^{1, 2}, and Stefan Filipp^{1, 2} — ¹Technical University of Munich, TUM School of Natural Sciences, Physics Department, Garching, Germany — ²Walther-Meißner-Institut, Bayerische Akademie der Wissenschaften, Garching, Germany — ³Peak Quantum GmbH, Garching, Germany

Scaling superconducting quantum processors requires fabrication processes that maintain high qubit coherence across increasingly complex multi-qubit chips. While substantial progress has been achieved for isolated, single-qubit devices, preserving these coherence levels in multi-qubit architectures remains challenging due to added fabrication steps and potential loss mechanisms. In particular, as system performance is frequently limited by the least coherent qubit, understanding coherence variations across a wafer is crucial. Therefore, we present coherence measurements from twelve transmon qubits across two chips fabricated on a 100 mm wafer. The qubits exhibit an average relaxation time of T₁ = 236 ± 14 µs, with the lowest device having a relaxation time of 111 ± 30 µs. We further examine the influence of fabrication processes required for large-scale integration, such as air bridges and indium bumps, on coherence. These lead to a reduction in coherence time, providing insight into the impact of additional processing required for large-scale superconducting quantum processors.

Keywords: Superconducting Qubits; Fabrication