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T: Fachverband Teilchenphysik

T 49: Electronics, Trigger, DAQ II

T 49.6: Vortrag

Mittwoch, 18. März 2026, 17:30–17:45, KH 00.023

Enabling lpGBT Interface Prototyping with a New FPGA Mezzanine Card — •Dmitry Eliseev, Nils Esper, Carsten Presser, Markus Merschmeyer, Alexander Schmidt, and Thomas Hebbeker — III. Physikalisches Institut A, RWTH Aachen University

The lpGBT (Low Power GigaBit Transceiver) is a radiation-tolerant ASIC developed to provide robust, high-speed, bidirectional optical links for the next generation of high-energy physics experiments. It is dedicated to communicate via optical links and supports transfer rates up to 10 Gb/s. The chip integrates Timing and Trigger Control (TTC), Data Acquisition (DAQ), and Slow Control (SC) data streams into a single constant-latency link. This unified architecture enables reliable transmission of timing, trigger, control, and monitoring information between the counting room and on-detector electronics, even in the harsh radiation environment of the LHC.

This talk introduces a newly developed FMC mezzanine board that provides an accessible and flexible platform for working with the lpGBT ASIC. It gives engineers and researchers a practical way to explore, test, and integrate the lpGBT into their detector readout and control systems. With the ready to use electrical and firmware interfaces, the board supports early development without requiring a full custom electronic and firmware design.

The talk gives an overview of the board's design features, from the optical SFP link to the on-board switches for selecting lpGBT working modes. It also presents a brief overview of the IP cores for interfacing.

Keywords: lpGBT; FPGA Mezzanine Card; Detector Front-End Interface; High-Speed Serial Link; Radiation hardent ASIC