Berlin 2008 – wissenschaftliches Programm
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DS: Fachverband Dünne Schichten
DS 22: High-k Dielectric Materials - Synthesis, Properties, Applications
DS 22.4: Vortrag
Mittwoch, 27. Februar 2008, 18:00–18:15, H 2032
Structural, chemical and electrical characterization of HfNO-HfTiO high-k dielectric stack — Visorian Mikhelashvili1, Gadi Eisenstein1, Thangadurai Paramasivam2, and •Wayne Kaplan2 — 1Electrical Engineering Dept. Technion — 2Material Engineering Dept.Technion
We study the influence of annealing temperature on structural, compositional and electrical characteristics of a MOS structure with a high-k dielectric based on a 5 nm HfNO-HfTiO nanolaminate stack. A common feature of all samples independent on annealing temperature is the observation of two distinct ~2-2.5 and 2.3-2.5 nm thick layers, respectively for transition (close to Si substrate) and top layers. The transition layer is amorphous, while in the top layer some crystalline inclusions embedded into the amorphous matrix are observed. EDS line-scans and XPS analysis showed that the transition layer is similar to metal-Si-O-N or metal-Si-O. The minimum values of quantum mechanical corrected Effective Oxide Thickness close to 1.29 and 0.86 nm, respectively for structures with Au and Cr electrodes. A large reduction of leakage current density to 1.5X10-8 and 2.9X10-7 A/cm2, respectively for Au and Cr gate electrodes at an electric fields of 2 MV/cm was observed with annealing temperature and breakdown electric filed as high as ~10-12 MV/cm, was measured independently of the electrodes type.