Mainz 2014 – scientific programme

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T: Fachverband Teilchenphysik

T 121: DAQ, Trigger, Elektronik 5

T 121.3: Talk

Thursday, March 27, 2014, 17:15–17:30, GFH 01-731

Online data reduction with FPGA-based track reconstruction for the Belle II DEPFET Pixel Detector — •Michael Schnell, Jochen Dingfelder, and Carlos Marinas — University of Bonn

The innermost two layers of the Belle II vertex detector at the KEK facility in Tsukuba, Japan, will be covered by high-granularity DEPFET pixel sensors (PXD). The large number of pixels leads to a high data rate of around 256 Gbps, which has to be significantly reduced by the Data Acquisition System. For the data reduction the hit information of the surrounding Silicon strip Vertex Detector (SVD) is utilized to define so-called Regions of Interest (ROI). Only hit information of the pixels located inside these ROIs are saved. The ROIs for the PXD are computed by reconstructing track segments from SVD data and extrapolation to the PXD. The goal is to achive a data reduction of up to a factor of 10 with this ROI selection. All the necessary processing stages, the receiving, decoding and multiplexing of SVD data on 48 optical fibers, the track reconstruction and the definition of the ROIs, will be performed by the Data Concentrator. The planned hardware design is based on a distributed set of Advanced Mezzanine Cards (AMC) each equipped with a Field Programmable Gate Array (FPGA) chip and 4 optical transceivers.

In this talk, the hardware and the FPGA-based tracking algorithm is introduced with recent performance simulation results. In addition, the acquisition and pre-processing of the SVD data are discussed.