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T: Fachverband Teilchenphysik
T 94: DAQ, Trigger, Elektronik 4
T 94.2: Talk
Wednesday, March 26, 2014, 17:05–17:20, GFH 01-731
Firmware implementation of algorithms for the new topological processor in the ATLAS first level trigger — •Stephan Maldaner, Regina Caputo, Ulrich Schäfer, and Stefan Tapprogge — Universität Mainz, Staudingerweg 7, 55128 Mainz
After the upgrade in 2013/2014 of the Large Hadron Collider proton-proton collisions will be provided at a center-of-mass energy of up to 14 TeV with an instantaneous luminosity of at least 1· 1034 cm−2 s−1. During this upgrade a new FPGA based electronics system (Topological Processor) will be included in the ATLAS trigger chain to keep up with the increased rate of events. To increase the selectivity of the trigger this processor will make its decisions based upon topological criteria like angular cuts and mass calculations.
As a hardware based trigger it will have to fit into the tight first level trigger latency budget of 2.5 µs and thus provides the challenge of making decisions within very short time. Beside the latency the main constraints on the capabilities of the algorithms which will be implemented as firmware is the required amount of logic resources of the FPGA. Therefore to be able to use as much information as possible, each module will be equipped with 2 state-of-the-art Xilinx Virtex 7 FPGAs to process the incoming data. This talk will present an overview of the planned topological algorithms and discuss properties of their implementation in firmware.