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Q: Fachverband Quantenoptik und Photonik

Q 61: Quantum Optics (Miscellaneous)

Q 61.18: Poster

Thursday, March 17, 2022, 16:30–18:30, P

Implementation of a sub 10ps RMS jitter TDC in Xilinx 7-series FPGAs — •Verena Leopold¹, Yury Prokazov², Evgeny Turbin², Stefan Richter¹, and Joachim von Zanthier¹ — ¹FAU, Erlangen, Germany — ²Photonscore, Magdeburg, Germany

For many experiments in quantum optics, it is crucial to detect photon arrival times from (multiple) detectors. Usually a TDC (Time-to-Digital-Converter) is used for recording of this time stream. However for low-contrast, long-running measurements, available TDCs show disadvantages. The main challenges are high quality analog inputs and non-linearities on short ps-timescales. We successfully implemented a TDL (Tapped-Delay-Line) TDC inside an FPGA. Communication with the CPU is established by PCIe. Using Xilinx 7-series silicon, a RMS jitter of (3.24 ± 0.03) ps was obtained with non-linearities in the regime of 0.32%.