Berlin 2008 – wissenschaftliches Programm
Bereiche | Tage | Auswahl | Suche | Downloads | Hilfe
HL: Fachverband Halbleiterphysik
HL 15: Devices
HL 15.1: Vortrag
Montag, 25. Februar 2008, 11:15–11:30, ER 164
Disposable DotFET: Overlay requirements and the accuracy of E-Beam lithography on structures defined by optical lithography — •J. Moers1, J. Gerharz1, G. Mussler1, L.K. Nanver2, and D. Grützmacher1 — 1IBN and CNI, Research Center Jülich, 52425 Jülich, Germany — 2DIMES, Delft Technical University, Feldmannweg 17, 2628 CT Delft, The Netherlands
Strained silicon enhances carrier mobility and therefore has drawn increasing attention for application in MOSFET devices. While wafer size processes for SiGe pseudosubstrates need either thick epitaxial layers or sophisticated processing, the ordered growth of Ge dots only needs a simple prepatterning of the substrate. In a self organized growth on a prepatterned substrate the Ge dots will grow in the etched seedholes, only. Onto these substrates a silicon capping layer is grown, which will be strained only on top of the Ge dots.
To utilize the strain it is indispensable to align the active area of the device on the Ge dot. In the European project D-DotFET the seedholes are defined by optical lithography, while for critical overlay steps, such as the source and drain extensions and the gate, e-beam lithography is used. To ensure an accurate overlay it is necessary to investigate the single components for their overlay accuracy and the accuracy of the interplay of the components. Furthermore it has to be examined, if the influence of the process will hamper the overlay accuracy.
Results for the overlay accuracy for the D-DotFET process show that the requirements can be fulfilled by using a proper marker layout and a process, which will conserve the markers.